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1 LTC3737 3737fa dual 2-phase, no r sense tm , dc/dc controller with output tracking figure 1. high efficiency, 2-phase, 550khz dual step-down converter sense resistor optional out-of-phase controllers reduce required input capacitance programmable output voltage tracking constant frequency current mode architecture wide v in range: 2.75v to 9.8v wide v out range: 0.6v to v in 0.6v 1.5% reference low dropout operation: 100% duty cycle true pll for frequency locking or adjustment (frequency range 250khz to 850khz) selectable burst mode ? or pulse skipping operation at light loads internal soft-start circuitry selectable maximum peak current sense threshold power good output voltage monitor output overvoltage protection micropower shutdown: i q = 9 a tiny 4mm 4mm qfn and 24-lead ssop packages one or two lithium-ion powered devices notebook and palmtop computers, pdas portable instruments distributed dc power systems the ltc ? 3737 is a 2-phase dual step-down switching regulator controller that requires few external compo- nents. the constant frequency current mode architecture provides excellent ac and dc load and line regulation. mosfet v ds sensing eliminates the need for current sense resistors and improves efficiency. power loss and noise due to the esr of the input capacitance are mini- mized by operating the two controllers out of phase. burst mode operation provides high efficiency operation at light loads. 100% duty cycle provides low dropout operation and extends battery operating time. switching frequency can be programmed up to 750khz, allowing the use of small surface mount inductors and capacitors. for noise sensitive applications, the LTC3737 can be externally synchronized from 250khz to 850khz. other features include a power good output voltage moni- tor, a tracking input and internal soft-start. the LTC3737 is available in the low profile thermally enhanced (4mm 4mm) qfn package or a 24-lead ssop narrow package. + + sw1 v fb1 i th1 pgood sgnd track i th2 v fb2 sw2 sense1 + pv in1 pgate1 v in pgnd run/ss pgate2 pv in2 sense2 + LTC3737 15k m1 2.2 h 2.2 h m2 d1 47 f 10 f 2 v in 2.75v to 9.8v v out1 2.5v v out2 1.8v 47 f 3737 f01 d2 59k 187k 59k 118k 15k 220pf 220pf descriptio u features applicatio s u typical applicatio u load current (ma) efficiency (%) 100 95 90 85 80 75 70 65 60 1 100 1000 10000 3737 f01b 10 10000 1000 100 10 1 power loss (mw) efficiency v out = 1.8v v out = 2.5v v in = 3.3v typical power loss (v out = 2.5v) efficiency and power loss vs load current , ltc and lt are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5731694, 5929620, 6144194, 6580258, 5994885
2 LTC3737 3737fa 24 23 22 21 20 19 7 8 9 top view 25 uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 i th1 iprg2 plllpf sgnd v in track pgate1 pgnd pgate2 run/ss nc v fb1 iprg1 sense1 + pv in1 nc v fb2 i th2 pgood sense2 + pv in2 sw1 (sense1 C ) sw2 (sense2 C ) sync/ mode input supply voltage (v in ), pv in1 , pv in2 , sense1 + , sense2 + .................................. C 0.3v to 10v pgate1, pgate2, plllpf, run/ss, sync/mode, track, iprg1, iprg2 voltages .... C 0.3v to (v in + 0.3v) v fb1 , v fb2 , i th1 , i th2 voltages .................. C 0.3v to 2.4v sw1, sw2 voltages ............ C2v to v in + 1v or 10v max pgood ..................................................... C 0.3v to 10v pgate1, pgate2 peak output current (<10 s) ......... 1a absolute axi u rati gs w ww u package/order i for atio uu w t jmax = 125 c, ja = 130 c/w order part number LTC3737egn consult ltc marketing for parts specified with wider operating temperature ranges. operating temperature range (note 2) ... C40 c to 85 c storage ambient temperature range qfn package .................................... C65 c to 125 c ssop package .................................. C65 c to 150 c junction temperature (note 3) ............................ 125 c lead temperature (soldering, 10sec) LTC3737egn ................................................... 300 c (note 1) order part number 3737 LTC3737euf uf part marking t jmax = 125 c, ja = 37 c/w exposed pad is pgnd (pin 25) must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 top view sw1 (sense1 C ) sw2 (sense2 C ) gn package 24-lead (narrow) plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 iprg1 v fb1 i th1 iprg2 plllpf sgnd v in track v fb2 i th2 pgood sense1 + pv in1 nc sync/mode pgate1 pgnd pgate2 run/ss nc pv in2 sense2 + electrical characteristics the denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 4.2v unless otherwise specified. parameter conditions min typ max units main control loops input dc supply current (note 4) sleep mode 220 325 a shutdown run/ss = 0v 9 20 a uvlo v in < uvlo threshold C200mv 3 10 a undervoltage lockout threshold v in falling 1.95 2.25 2.55 v v in rising 2.15 2.45 2.75 v shutdown threshold at run/ss 0.45 0.65 0.85 v start-up current source run/ss = 0v 0.4 0.7 1 a regulated feedback voltage 0 c to 85 c (note 5) 0.591 0.6 0.609 v C40 c to 85 c 0.588 0.6 0.612 v output voltage line regulation 2.75v < v in < 9.8v (note 5) 0.05 0.2 mv/v
3 LTC3737 3737fa electrical characteristics the denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 4.2v unless otherwise specified. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LTC3737e is guaranteed to meet specified performance from 0 c to 70 c. specifications over the C40 c to 85 c operating range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja c/w) note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the LTC3737 is tested in a feedback loop that servos i th to a specified voltage and measures the resultant v fb voltage. note 6: peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in figure 2. parameter conditions min typ max units output voltage load regulation i th = 0.9v (note 5) 0.12 0.5 % i th = 1.7v C0.12 C0.5 % v fb1,2 input current (note 5) 10 50 na track input current track = 0.6v 10 50 na overvoltage protect threshold measured at v fb 0.66 0.68 0.7 v overvoltage protect hysteresis 20 mv gate drive 1, 2 rise time c l = 3000pf 40 ns gate drive 1, 2 fall time c l = 3000pf 40 ns maximum current sense voltage ( ? v sense(max) ) iprg = floating (note 6) 110 125 140 mv (sense + C sw) iprg = 0v (note 6) 70 85 100 mv iprg = v in (note 6) 185 204 223 mv soft-start time time for v fb1 to ramp from 0.05v to 0.55v 0.667 0.833 1 ms oscillator and phase-locked loop oscilator frequency unsynchronized (sync/mode not clocked) plllpf = floating 480 550 600 khz plllpf = 0v 260 300 340 khz plllpf = v in 650 750 825 khz phase-locked loop lock range sync/mode clocked minimum synchronizable frequency 200 250 khz maximum synchronizable frequency 850 1150 khz phase detector output current sinking f osc > f sync/mode C4 a sourcing f osc < f sync/mode 4 a pgood output pgood voltage low i pgood sinking 1ma 125 mv pgood trip level v fb with respect to set output voltage v fb < 0.6v, ramping positive C13 C10.0 C7 % v fb < 0.6v, ramping negative C16 C13.3 C10 % v fb > 0.6v, ramping negative 7 10.0 13 % v fb > 0.6v, ramping positive 10 13.3 16 %
4 LTC3737 3737fa typical perfor a ce characteristics uw efficiency vs load current load current (ma) 50 efficiency (%) 60 70 80 90 1 100 1000 10000 3737 g01 10 100 55 65 75 85 95 burst mode operation (sync/mode = v in ) pulse skipping (sync/mode = 0v) t a = 25 c v in = 3.3v v out = 2.5v figure 13 circuit load current (ma) 65 efficiency (%) 95 100 60 55 90 75 85 80 70 1 100 1000 10000 3737 g02 50 10 t a = 25 c v out = 2.5v v in = 3.3v v in = 5v v in = 4.2v v out ac-coupled 100mv/div v in = 3.3v 200 s/div 3737 g03 v out = 1.8v i load = 300ma to 3a sync/mode = v in figure 13 circuit i l 2a/div efficiency vs load current load step (burst mode operation) load step (pulse skipping mode) tracking start-up with internal soft-start (c ss = 0nf) tracking start-up with external soft-start (c ss = 10nf) v out ac-coupled 100mv/div v in = 3.3v 200 s/div 3737 g04 v out = 1.8v i load = 300ma to 3a sync/mode = 0v figure 13 circuit i l 2a/div v in = 4.2v 250 s/div 3737 g05 r load1 = r load2 = 1 ? figure 13 circuit 500mv/ div v out1 2.5v v out2 1.8v v in = 4.2v 2.5ms/div 3737 g06 r load1 = r load2 = 1 ? figure 13 circuit 500mv/ div v out1 2.5v v out2 1.8v regulated feedback voltage vs temperature temperature ( c) C60 feedback voltage (v) 0.601 0.603 0.605 100 3737 g07 0.599 0.597 0.591 C20 20 60 C40 0 40 80 0.595 0.593 0.609 0.607 temperature ( c) C60 115 maximum current sense threshold (mv) 120 125 130 135 C40 C20 0 20 3737 g08 40 60 80 100 i prg = float temperature ( c) C60 0 run/ss voltage (v) 0.1 0.3 0.4 0.5 1.0 0.7 C20 20 40 3737 g09 0.2 0.8 0.9 0.6 C40 0 60 80 100 maximum current sense threshold vs temperature shutdown (run) threshold vs temperature
5 LTC3737 3737fa typical perfor a ce characteristics uw undervoltage lockout threshold vs temperature temperature ( c) C60 input (v in ) voltage (v) 2.30 2.40 100 3737 g10 2.20 2.10 C20 20 60 C40 0 40 80 2.50 2.25 2.35 2.15 2.45 v in rising v in falling temperature ( c) C60 0.4 run/ss pull-up current ( a) 0.5 0.6 0.7 0.8 C20 20 60 100 3737 g11 0.9 1.0 C40 0 40 80 temperature ( c) C60 C10 nromalized frequency (%) C8 C4 C2 0 10 4 C20 20 40 3737 g12 C6 6 8 2 C40 0 60 80 100 run/ss pull-up current vs temperature oscillator frequency vs temperature oscillator frequency vs input voltage shutdown quiescent current vs input voltage run/ss start-up current vs input voltage input voltage (v) 2 C5 normalized frequency shift (%) C4 C2 C1 0 5 2 4 6 7 3737 g13 C3 3 4 1 35 8 9 10 t a = 25 c input voltage (v) 2 0 shutdown current ( a) 2 6 8 10 20 14 4 6 7 3737 g14 4 16 18 12 35 8 9 10 t a = 25 c run/ss = 0v input voltage (v) 2 run/ss pin start-up current ( a) 0.5 0.6 0.7 10 3737 g15 0.4 0.3 0 0.1 4 6 8 3 5 7 9 0.2 0.9 0.8 t a = 25 c run/ss = 0v
6 LTC3737 3737fa uu u pi fu ctio s i th1 , i th2 (pins 1, 8/pins 4, 11): current threshold and error amplifier compensation point. nominal operating range on these pins is from 0.7v to 2v. the voltage on this pin determines the threshold of the main current comparator. plllpf (pin 3/pin 6): frequency set/pll lowpass filter. when synchronizing to an external clock, this pin serves as the lowpass filter point for the phase-locked loop. nor- mally, a series rc is connected between this pin and ground. when not synchronizing to an external clock, this pin serves as the frequency select input. tying this pin to gnd selects 300khz operation; tying this pin to v in selects 750khz operation. floating this pin selects 550khz operation. sgnd (pin 4/pin 7): signal ground. this pin serves as the ground connection for most internal circuits. v in (pin 5/pin 8): chip signal power supply. this pin powers the entire chip except for the gate drivers. exter- nally filtering this pin with a lowpass rc network (e.g., r = 10 ? , c = 1 f) is suggested to minimize noise pickup, especially in high load current applications. track (pin 6/pin 9): tracking input for second control- ler. this pin allows the start-up of v out2 to track that of v out1 according to a ratio established by a resistor divider on v out1 connected to the track pin. for one-to-one tracking of v out1 and v out2 during start-up, a resistor divider with values equal to those connected to v fb2 from v out2 should be used to connect to track from v out1 . pgood (pin 9/pin 12): power good output voltage moni- tor open-drain logic output. this pin is pulled to ground when the voltage on either feedback pin (v fb1 , v fb2 ) is not within 13.3% of its nominal set point. nc (pins 13, 19/pins 16, 22): no connect. run/ss (pin 14/pin 17): run control input and optional external soft-start input. forcing this pin below 0.65v shuts down the chip (both channels). driving this pin to v in or releasing this pin enables the chip to start-up with the internal soft-start. an external soft-start can be pro- grammed by connecting a capacitor between this pin and ground. pgnd (pin 16/pin 19): power ground. this pin serves as the ground connection for the gate drivers. pgate1, pgate2 (pins 17, 15/pins 20, 18): gate drives for external p-channel mosfets. these pins have an output swing from pgnd to sense + . sync/mode (pin 18/pin 21): external clock synchroni- zation and burst mode/pulse skipping select. applying a clock with frequency between 250khz to 850khz causes the internal oscillator to phase lock to the external clock, and disables burst mode operation but allows pulse skip- ping at low load currents. forcing this pin high enables burst mode operation. forcing this pin low enables pulse- skipping mode. in these cases, the frequency of the internal oscillator is set by the voltage on the plllpf pin. do not let this pin float. pv in1 , pv in2 (pins 20, 12/pins 23, 15): powers of the gate drivers. sense1 + , sense2 + (pins 21, 11/pins 24, 14): positive inputs to differential current comparators. normally con- nected to the sources of the external p-channel mosfets. sw1 (sense1 ), sw2 (sense2 ) (pins 22, 10/pins 1, 13): switch node connections to inductors. also the negative inputs to differential peak current comparators. normally connected to the drains of the external p-chan- nel mosfets and the inductor when not using a sense resistor. when a sense resistor is used, it will be con- nected between sw and sense + . iprg1, iprg2 (pins 23, 2/pins 2, 5): three-state pins to select maximum peak sense voltage threshold. these pins select the maximum allowed voltage drop between the sense + and sw pins (i.e., the maximum allowed drop across the external p-channel mosfet) for each channel. tie high, low or float to select 204mv, 85mv or 125mv, respectively. v fb1 , v fb2 (pins 24, 7/pins 3, 10): each receives the remotely sensed feedback voltage for its controller from an external resistive divider across the output. exposed pad (pin 25/na): exposed pad is pgnd and must be soldered to pcb. (qfn/ssop)
7 LTC3737 3737fa pgate1 pgnd i th1 0.68v 0.12v v in ov1 pgood1 i th1 i th2 duplicate for second channel 0.54v v fb1 soft-start v ref = 0.6v v ref = 0.6v track v fb2 r2b r2a v out2 r c c c 3737 bd ov1 sleep1 sc1 C + C + C + + C + switching logic and blanking circuit C + C + C + 0.15v burstdis 0.3v q clk1 slope1 m1 d1 l1 s r sense1 + iprog1 pv in1 sw1 v in c in v in i cmp voltage controlled oscillator undervoltage lockout 0.7 a t = 1ms internal soft-start v in voltage reference clk1 slope1 burstdis slope2 pgood1 pgood2 uvsd clk2 slope comp phase detector sync/mode plllpf run/ss v in pgood uv uvsd cmsd v ref 0.6v sgnd clock detect burst defeat ovp scp c out v out1 c ss soft- start extss intss r1a r1b r trackb r tracka C + + eamp1 eamp2 C + + mux v fb fu ctio al diagra u u w
8 LTC3737 3737fa operatio u (refer to functional diagram) main control loop the LTC3737 uses a constant frequency, current mode architecture with the two controller channels operating 180 degrees out of phase. during normal operation, each external p-channel power mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the current comparator (i cmp ) resets the latch. the peak inductor current at which i cmp resets the rs latch is determined by the voltage on the i th pin, which is the output of each error amplifier (eamp). the v fb pin re- ceives the output voltage feedback signal from an external resistor divider. this feedback signal is compared to the internal 0.6v reference voltage by the eamp. when the load current increases, it causes a slight decrease in v fb relative to the 0.6v reference, which in turn, causes the i th voltage to increase until the average inductor current matches the new load current. shutdown, soft-start and tracking start-up (run/ss and track pins) the LTC3737 is shut down by pulling the run/ss pin low. in shutdown, all controller functions are disabled and the chip draws only 9 a. the pgate outputs are held high (off) in shutdown. releasing run/ss allows an internal 0.7 a current source to charge up the run/ss pin. when the run/ss pin reaches 0.65v, the LTC3737s two con- trollers are enabled. the start-up of v out1 is controlled by the LTC3737s internal soft-start. during soft-start, the error amplifier eamp compares the feedback signal v fb1 to the internal soft-start ramp (instead of the 0.6v reference), which rises linearly from 0v to 0.6v in about 1ms. this allows the output voltage to rise smoothly from 0v to its final value, while maintaining control of the inductor current. the 1ms soft-start time can be increased by connecting the optional external soft-start capacitor, c ss , between the run/ss and sgnd pins. as the run/ss pin continues to rise linearly from approximately 0.65v to 1.3v (being charged by the internal 0.7 a current source), the eamp regulates v fb1 linearly from 0v to 0.6v. the start-up of v out2 is controlled by the voltage on the track pin. when the voltage on the track pin is less than the 0.6v internal reference, the LTC3737 regulates the v fb2 voltage to the track pin instead of the 0.6v reference. typically, a resistor divider on v out1 is con- nected to the track pin to allow the start-up of v out2 to track that of v out1 . for one-to-one tracking during start- up, the resistor divider would have the same values as the divider on v out2 that is connected to v fb2 . if no tracking function is desired, then the track pin can be tied to v in . note, however, that in this situation, there would be no (internal or external) soft-start on v out2 . light load operation (burst mode operation or pulse skipping mode) (sync/mode pin) the LTC3737 can be enabled to enter high efficiency burst mode operation at low load currents. to select burst mode operation, tie the sync/mode pin to a dc voltage above 0.6v (e.g., v in ). to disable burst mode operation and enable pwm pulse skipping mode, connect sync/mode to a dc voltage below 0.6v (e.g., sgnd). in this mode, the efficiency is lower at light loads. however, pulse skipping mode has the advantages of lower output ripple and less interference to audio circuitry. when a controller is in burst mode operation, the peak current in the inductor is set to approximate one-fourth of the maximum sense voltage even when the voltage on the i th pin indicates a lower value. if the average inductor current is greater than the load current, the eamp will decrease the voltage on the i th pin. when the i th voltage drops below 0.85v, the internal sleep signal goes high and the external mosfet is turned off. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3737 draws. the load current is supplied by the output capacitor. as the output voltage decreases, the eamp increases the i th voltage. when the i th voltage reaches 0.925v, the sleep signal goes low and the controller resumes normal opera- tion by turning on the external p-channel mosfet on the next cycle of the internal oscillator. when the sync/mode pin is clocked by an external clock source to use the phase-locked loop (see frequency selection and phase-locked loop), the LTC3737 operates in pwm pulse skipping mode at light loads.
9 LTC3737 3737fa operatio u (refer to functional diagram) when a controller is in pulse skipping operation, an internal offset at the current comparator input will assure that the current comparator remains tripped even at zero load current and the regulator will start to skip cycles, as it must, in order to maintain regulation. short-circuit protection when one of the outputs is shorted to ground (v fb < 0.12v), the switching frequency of that controller is re- duced to 1/3 of the normal operating frequency. the other controller is unaffected and maintains normal operation. the short-circuit threshold on v fb2 is based on the smaller of 0.12v and a fraction of the voltage on the track pin. this also allows v out2 to start up and track v out1 more easily. note that if v out1 is truly short circuited (v out1 = v fb1 = 0v), then the LTC3737 will try to regulate v out2 to 0v if a resistor divider on v out1 is connected to the track pin. output overvoltage protection as a further protection, the overvoltage comparator (ovp) guards against transient overshoots, as well as other more serious conditions, that may overvoltage the output. when the feedback voltage on the v fb pin has risen 13.33% above the reference voltage of 0.6v, the external p-chan- nel mosfet is turned off until the overvoltage is cleared. frequency selection and phase-locked loop (plllpf and sync/mode pins) the selection of switching frequency is a tradeoff between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to main- tain low output ripple voltage. the switching frequency of the LTC3737s controllers can be selected using the plllpf pin. if the sync/mode pin is not being driven by an external clock source, the plllpf pin can be floated, tied to v in or tied to sgnd to select 550khz, 750khz or 300khz, respectively. a phase-locked loop (pll) is available on the LTC3737 to synchronize the internal oscillator to an external clock source that is connected to the sync/mode pin. in this case, a series rc should be connected between the plllpf pin and sgnd to serve as the plls loop filter. the LTC3737 phase detector adjusts the voltage on the plllpf pin to align the turn-on of controller 1s external p-channel mosfet to the rising edge of the synchronizing signal. thus, the turn-on of controller 2s external p-channel mosfet is 180 degrees out of phase to the rising edge of the external clock source. the typical capture range of the LTC3737s phase-locked loop is from approximately 200khz to 1mhz, with a guarantee over all variations and temperature to be be- tween 250khz and 850khz. in other words, the LTC3737s pll is guaranteed to lock to an external clock source whose frequency is between 250khz and 850khz. dropout operation when the input supply voltage (v in ) decreases towards the output voltage, the rate of change of the inductor current while the external p-channel mosfet is on (on cycle) decreases. this reduction means that the p-channel mosfet will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by the eamp on the i th pin. further reduction in the input supply voltage will eventually cause the p-channel mosfet to be turned on 100%; i.e., dc. the output voltage will then be determined by the input voltage minus the voltage drop across the p-channel mosfet and the inductor. undervoltage lockout to prevent operation of the p-channel mosfet below safe input voltage levels, an undervoltage lockout is incorpo- rated in the LTC3737. when the input supply voltage (v in ) drops below 2.25v, the external p-channel mosfet and all internal circuitry are turned off except for the undervolt- age block, which draws only a few microamperes.
10 LTC3737 3737fa operatio u (refer to functional diagram) peak current sense voltage selection and slope compensation (iprg1 and iprg2 pins) when a controller is operating below 20% duty cycle, the peak current sense voltage (between the sense + and sw pins) allowed across the external p-channel mosfet is determined by: ? = () v av v sense max ith () C. 07 10 where a is a constant determined by the state of the iprg pins. floating the iprg pin selects a = 1; tying iprg to v in selects a = 5/3; tying iprg to sgnd selects a = 2/3. the maximum value of v ith is typically about 1.98v, so the maximum sense voltage allowed across the external p-channel mosfet is 125mv, 85mv or 204mv for the three respective states of the iprg pin. the peak sense voltages for the two controllers can be independently selected by the iprg1 and iprg2 pins. however, once the controllers duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor given by the curve in figure 2. the peak inductor current is determined by the peak sense voltage and the on-resistance of the external p-channel mosfet: i v r pk sense max ds on = ? () () power good (pgood) pin a window comparator monitors both feedback voltages and the open-drain pgood output pin is pulled low when either or both feedback voltages are not within 10% of the 0.6v reference voltage. pgood is low when the LTC3737 is shutdown or in undervoltage lockout. 2-phase operation why the need for 2-phase operation? until recently, con- stant frequency dual switching regulators operated both controllers in phase (i.e., single phase operation). this means that both topside mosfets (p-channel) are turned on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. these large amplitude pulses increase the total rms current flowing in the input capaci- tor, requiring the use of larger and more expensive input capacitors, and increase both emi and power losses in the input capacitor and input power supply. with 2-phase operation, the two controllers of the LTC3737 are operated 180 degrees out of phase. this effectively interleaves the current pulses coming from the topside mosfet switches, greatly reducing the time where they overlap and add together. the result is a significant reduction in the total rms current, which in turn allows the use of smaller, less expensive input capacitors, reduces shielding requirements for emi and improves real world operating efficiency. figure 3 shows qualitatively example waveforms for a single phase dual controller versus a 2-phase LTC3737 system. in this case, 2.5v and 1.8v outputs, each drawing figure 2. maximum peak current vs duty cycle duty cycle (%) 10 sf = i/i max (%) 60 80 110 100 90 3737 f02 40 20 50 70 90 30 10 0 30 50 70 20 0 40 60 80 100
11 LTC3737 3737fa operatio u (refer to functional diagram) a load current of 2a, are derived from a 7v (e.g., a 2-cell li-ion battery) input supply. in this example, 2-phase operation would reduce the rms input capacitor current from 1.79a rms to 0.91a rms . while this is an impressive reduction by itself, remember that power losses are pro- portional to i rms 2 , meaning that actual power wasted is reduced by a factor of 3.86. the reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances, and pro- tection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. significant cost and board footprint savings are also realized by being able to use smaller, less expensive, lower rms current-rated, input capacitors. of course the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two control- lers, which in turn are dependent upon the input supply voltage. figure 4 depicts how the rms input current varies for single phase and 2-phase dual controllers with 2.5v and 1.8v outputs over a wide input voltage range. single phase dual controller 2-phase dual controller sw1 (v) sw2 (v) i l1 i l2 i in 3737 f03 input voltage (v) 2 0 input capacitor rms current 0.2 0.6 0.8 1.0 2.0 1.4 4 6 7 3737 f04 0.4 1.6 1.8 1.2 35 8 9 10 single phase dual controler 2-phase dual controler v out1 = 2.5v/2a v out2 = 1.8v/2a figure 4. rms input current comparison figure 3. example waveforms for a single phase dual controller vs the 2-phase LTC3737 it can be readily seen that the advantages of 2-phase operation are not limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle.
12 LTC3737 3737fa applicatio s i for atio wu uu the typical LTC3737 application circuit is shown in figure 1. external component selection for each of the LTC3737s controllers is driven by the load requirement and begins with the selection of the inductor (l) and the power mosfet m1. next, the output diode d1 is selected. finally c in and c out are chosen. power mosfet selection an external p-channel mosfet must be selected for use with each channel of the LTC3737. the main selection criteria for the power mosfet are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss and the total gate charge q g . the gate drive voltage is the input supply voltage. since the LTC3737 is designed for operation down to low input voltages, a sublogic level mosfet (r ds(on) guaranteed at v gs = 2.5v) is required for applications that work close to this voltage. when these mosfets are used, make sure that the input supply to the LTC3737 is less than the abso- lute maximum mosfet v gs rating, which is typically 8v. the p-channel mosfets on-resistance is chosen based on the required load current. the maximum average output load current, i out(max) , is equal to the peak induc- tor current minus half the peak-to-peak ripple current, i ripple . the LTC3737s current comparator monitors the drain-to-source voltage, v ds , of the p-channel mosfet, which is sensed between the sense + and sw pins. the peak inductor current is limited by the current threshold, set by the voltage on the i th pin, of the current comparator. the voltage on the i th pin is internally clamped, which limits the maximum current sense threshold ? v sense(max) to approximately 125mv when iprg is floating (85mv when iprg is tied low; 204mv when iprg is tied high). the output current that the LTC3737 can provide is given by: i v r i out max sense max ds on ripple () () () C = ? 2 where i ripple is the inductor peak-to-peak ripple current (see inductor value calculation). a reasonable starting point is setting ripple current i ripple to be 40% of i out(max) . rearranging the above equation yields: r v i ds on max sense max out max ()( ) () () ? = ? 5 6 for duty cycle < 20% however, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of r ds(on) to provide the required amount of load current: rsf v i ds on max sense max out max ()( ) () () ?? = ? 5 6 where sf is a scale factor whose value is obtained from the curve in figure 2. these must be further derated to take into account the significant variation in on-resistance with temperature. the following equation is a good guide for determining the required r ds(on)max at 25 c (manufacturers specifica- tion), allowing some margin for variations in the LTC3737 and external component values: rsf v i ds on max sense max out max t ()( ) () () ?.? ? ? = ? 5 6 09 the t is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/ c, as shown in figure 5. junction to case temperature t jc is figure 5. r ds(on) vs temperature junction temperature ( c) C50 t normalized on resistance 1.0 1.5 150 3737 f05 0.5 0 0 50 100 2.0
13 LTC3737 3737fa applicatio s i for atio wu uu about 10 c in most applications. for a maximum ambient temperature of 70 c, using 80 c ~ 1.3 in the above equation is a reasonable choice. the power dissipated in the mosfet strongly depends on its respective duty cycles and load current. when the LTC3737 is operating in continuous mode, the duty cycles for the mosfet are: duty cycle = v out + + v vv d in d the mosfet power dissipations at maximum output current are: p p = + + () + vv vv ir vi c f out d in d out max t ds on in out max rss osc ???? ??? () () () 2 2 2 r the mosfet has i 2 r losses and the p p equation includes an additional term for transition losses, which are largest at high input voltages. using a sense resistor a sense resistor r sense can be connected between sense + and sw to sense the output load current. in this case, the source of the p-channel mosfet is connected to the sw pin and the drain is not connected to any pin of the LTC3737. therefore, the current comparator monitors the voltage developed across r sense instead of v ds of the p-channel mosfet. the output current that the LTC3737 can provide in this case is given by: i v r i out max sense max sense ripple () () C = ? 2 setting ripple current as 40% of i out(max) and using figure 2 to choose sf, the value of r sense is: rsf v i sense sense max out max = ? 5 6 ?? () () (see the r ds(on) selection in power mosfet selection). variation in the resistance of a sense resistor is much smaller than the variation in on-resistance of the external mosfet. therefore the load current is well controlled, and the system is more stable with a sense resistor. however the sense resistor causes extra i 2 r losses in addition to the i 2 r losses of the mosfet. therefore, using a sense resistor lowers the efficiency of LTC3737, especially for large load current. operating frequency and synchronization the choice of operating frequency, f osc , is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switch- ing losses, both gate charge loss and transition loss. however, lower frequency operation requires more induc- tance for a given amount of ripple current. the internal oscillator for each of the LTC3737s control- lers runs at a nominal 550khz frequency when the plllpf pin is left floating and the sync/mode pin is a dc low or high. pulling the plllpf to v in selects 750khz operation; pulling the plllpf to gnd selects 300khz operation. alternatively, the LTC3737 will phase lock to a clock signal applied to the sync/mode pin with a frequency between 250khz and 850khz (see phase-locked loop and fre- quency synchronization). inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: ivv vvvv fl ripple in out out d in d osc = () + () + () ? ? ? ? ? ? C / ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max). note that the largest ripple current occurs at the highest input voltage. to guarantee
14 LTC3737 3737fa applicatio s i for atio wu uu kool m is a registered trademark of magnetics, inc. that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l vv fi vv vv in out osc ripple out d in d + + C ? ? burst mode operation considerations the choice of r ds(on) and inductor value also determines the load current at which the LTC3737 enters burst mode operation. when bursting, the controller clamps the peak inductor current to approximately: i v r burst peak sense max ds on () () () ? = ? 1 4 the corresponding average current depends on the amount of ripple current. lower inductor values (higher i ripple ) will reduce the load current at which burst mode operation begins. the ripple current is normally set so that the inductor current is continuous during the burst periods. therefore, i ripple i burst(peak) this implies a minimum inductance of: l vv fi vv vv min in out osc burst peak out d in d + + C ? ? () a smaller value than l min could be used in the circuit, although the inductor current will not be continuous during burst periods, which will result in slightly lower efficiency. in general, though, it is a good idea to keep i ripple comparable to i burst(peak) . inductor core selection once the value of l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m ? cores. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will in- crease. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design cur- rent is exceeded. core saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m . toroids are very space efficient, especially when several layers of wire can be used, while inductors wound on bobbins are generally easier to sur- face mount. however, designs for surface mount that do not increase the height significantly are available from coiltronics, coilcraft, dale and sumida. output diode selection the catch diode carries load current during the switch off time of the power mosfets . the average diode current is therefore dependent on the p-channel mosfet duty cycle. at high input voltages, the diode conducts most of the time. as v in approaches v out , the diode conducts for only a small fraction of the time. the most stressful condition for the diode is when the output is short circuited. under this condition, the diode must safely handle i peak at close to 100% duty cycle. therefore, it is important to ad- equately specify the diode peak current and average power dissipation so as not to exceed the diodes ratings. under normal conditions, the average current conducted by the diode is: i vv vv i d in out in d out = + C ? the allowable forward voltage drop in the diode is calcu- lated from the maximum short-circuit current as: v p i f d peak
15 LTC3737 3737fa applicatio s i for atio wu uu where p d is the allowable power dissipation and will be determined by efficiency and/or thermal requirements. a schottky diode is a good choice for low forward drop and fast switching time. remember to keep lead length short and observe proper grounding to avoid ringing and increased dissipation. c in and c out selection the selection of c in is simplified by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the control- ler with the highest v out ? i out product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output cur- rent drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle (v out + v d )/ (v in + v d ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c i vv vvvv in max in d out d in out required i rms + + ()( ) [] C / 12 this formula has a maximum at v in = 2v out + v d , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufactur- ers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC3737, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the LTC3737 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calcu- lated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resis- tance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the sources of the p-channel mosfets should be placed within 1cm of each other and share a common c in (s). separating the sourced and c in may produce undesirable voltage and current resonances at v in . a small (0.1 f to 1 f) bypass capacitor between the chip v in pin and ground, placed close to the LTC3737, is also suggested. a 10 ? resistor placed between c in and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( ? v out ) is approximated by: ? + ? ? ? ? ? ? v i esr fc out ripple out 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage.
16 LTC3737 3737fa applicatio s i for atio wu uu setting output voltage the LTC3737 output voltages are each set by an external feedback resistor divider carefully placed across the out- put, as shown in figure 6. the regulated output voltage is determined by: vv r r out b a =+ ? ? ? ? ? ? 06 1 .? during soft-start, the start-up of v out1 is controlled by slowly ramping the positive reference to the error amplifier from 0v to 0.6v, allowing v out1 to rise smoothly from 0v to its final value. the default internal soft-start time is 1ms. this can be increased by placing a capacitor between the run/ss pin and sgnd. in this case, the soft start time will be approximately: tc mv a ss ss 1 600 07 = ? . tracking the start-up of v out2 is controlled by the voltage on the track pin. normally this pin is used to allow the start-up of v out2 to track that of v out1 as shown qualitatively in figures 8a and 8b. when the voltage on the track pin is less than the internal 0.6v reference, the LTC3737 regu- lates the v fb2 voltage to the track pin voltage instead of 0.6v. the start-up of v out2 may ratiometrically track that of v out1 , according to a ratio set by a resistor divider (figure 8c): v v ra r rr rb ra out out tracka tracka trackb 1 2 2 22 = + + ? for coincident tracking (v out1 = v out2 during start-up), r2a = r tracka r2b = r trackb the ramp time for v out2 to rise from 0v to its final value is: tt r ra ra rb rr ss ss tracka tracka trackb 21 1 11 = + + ?? figure 7. run/ss pin interfacing figure 6. setting output voltage 1/2 LTC3737 v fb v out r b r a 3737 f06 run/soft start function the run/ss pin is a dual purpose pin that provides the optional external soft-start function and a means to shut down the LTC3737. pulling the run/ss pin below 0.65v puts the LTC3737 into a low quiescent current shutdown mode (i q = 9 a). if run/ss has been pulled all the way to ground, there will be a delay before the LTC3737 comes out of shutdown and is given by: tv c a sfc delay ss ss = = 065 07 093 .? . ./? this pin can be driven directly from logic as shown in figure 7. diode d1 in figure 7 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. this diode (and capacitor) can be deleted if the external soft-start is not needed. 3.3v or 5v run/ss run/ss c ss c ss d1 3737 f07 figure 8a. using the track pin LTC3737 v fb2 v out2 v out1 v fb1 track r2b r2a 3737 f08a r1b r1a r tracka r trackb
17 LTC3737 3737fa applicatio s i for atio wu uu for coincident tracking, tt v v ss ss out f out f 21 2 1 = ? where v out1f and v out2f are the final, regulated values of v out1 and v out2 . v out1 should always be greater than v out2 when using the track pin. if no tracking function is desired, then the track pin may be tied to v in . how- ever, in this situation there would be no (internal nor external) soft-start on v out2 . phase-locked loop and frequency synchronization the LTC3737 has a phase-locked loop (pll) comprised of an internal voltage controlled oscillator (vco) and a phase detector. this allows the turn-on of the external p-channel mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the sync/mode pin. the turn-on of controller 2s external p-channel mosfet is thus 180 degrees out of phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the external filter network connected to the plllpf pin. the relation- ship between the voltage on the plllpf pin and operating frequency, when there is a clock signal applied to sync/ mode, is shown in figure 9 and specified in the electrical characteristics table. note that the LTC3737 can only be synchronized to an external clock whose frequency is within range of the LTC3737s internal vco, which is nominally 200khz to 1mhz. this is guaranteed over tem- perature and variations to be between 250khz and 850khz. a simplified block diagram is shown in figure 10. figure 9. relationship between oscillator frequency and voltage at the plllpf pin figure 10. phase-locked loop block diagram digital phase/ frequency detector oscillator 2.4v r lp c lp 3737 f08 plllpf external oscillator sync/ mode plllpf pin voltage (v) 0 0 frequency (khz) 0.5 1 1.5 2 3737 f09 2.4 200 400 600 800 1000 1200 1400 time (8b) coincident tracking v out1 v out2 output voltage time 3737 f08b,c (8c) ratiometric tracking v out1 v out2 output voltage figures 8b and 8c. two different modes of output voltage tracking
18 LTC3737 3737fa applicatio s i for atio wu uu if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced con- tinuously from the phase detector output, pulling up the plllpf pin. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the plllpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the plllpf pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor c lp holds the voltage. the loop filter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01 f. typically, the external clock (on the sync/mode pin) input high level is 1.6v, while the input low level is 1.2v. these levels are guaranteed to be ttl/cmos compatible: 0.8v is guaranteed low, while 2.0v is guaranteed high. table 1 summarizes the different states in which the plllpf pin can be used. table 1 plllpf pin sync/mode pin frequency 0v dc voltage 300khz floating dc voltage 550khz v in dc voltage 750khz rc loop filter clock signal phase-locked to external clock fault condition: short circuit and current limit to prevent excessive heating of the catch diode, foldback current limiting can be added to reduce the current in proportion to the severity of the fault. foldback current limiting is implemented by adding di- odes d fb1 and d fb2 between the output and the i th pin as shown in figure 11. in a hard short (v out = 0v), the current will be reduced to approximately 50% of the maximum output current. low supply operation although the LTC3737 can function down to below 2.4v, the maximum allowable output current is reduced as v in decreases below 3v. figure 12 shows the amount of change as the supply is reduced down to 2.4v. also shown is the effect on v ref . figure 12. line regulation of v ref and maximum sense voltage input voltage (v) 75 normalized voltage or current (%) 85 95 105 80 90 100 2.2 2.4 2.6 2.8 3737 f12 3.0 2.1 2.0 2.3 2.5 2.7 2.9 v ref maximum sense voltage figure 11. foldback current limiting + 1/2 LTC3737 v fb i th r2 d fb1 v out d fb2 3737 f11 r1 minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the LTC3737 is capable of turning the top p-channel mosfet on and then off. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. the minimum on-time for the LTC3737 is typically about 280ns. low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: t vv fvv on min out d osc in d () ? < + + ()
19 LTC3737 3737fa applicatio s i for atio wu uu if the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3737 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% - (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in LTC3737 circuits: 1) LTC3737 dc bias current, 2) mosfet gate charge current, 3) i 2 r losses, 4) voltage drop of the output diode and 5) transition losses. 1) the v in (pin) current is the dc supply current, given in the electrical characteristics, that excludes mosfet driver currents. v in current results in a small loss that increases with v in . 2) mosfet gate charge current results from switching the gate capacitance of the power mosfet. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from pv in to ground. the resulting dq/dt is a current out of pv in , which is typically much larger than the dc supply current. in continuous mode, i gatechg = f ? q p . 3) i 2 r losses are calculated from the dc resistances of the mosfet, inductor and sense resistor. in continuous mode, the average output current flows through l but is chopped between the p-channel mosfet and the output diode. the mosfet r ds(on) multiplied by duty cycle can be summed with the resistance of l to obtain i 2 r losses. 4) the output diode is a major source of power loss at high currents and is worse at high input voltages. the diode loss is calculated by multiplying the forward voltage times the load current times the diode duty cycle. 5) transition losses apply to the external mosfet and increase with higher operating frequencies and input voltages. transition losses can be estimated from: transition loss = 2(v in ) 2 ? i o(max) ? c rss (f) other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( ? i load )(esr), where esr is the effective series resistance of cout . ? i load also begins to charge or dis- charge c out , which generates a feedback error signal. the regulator loop then returns v out to its steady-state value. during this recovery time, v out can be monitored for over- shoot or ringing. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the i th series r c -c c filter (see functional diagram) sets the dominant pole-zero loop compensation. the i th exter- nal components shown in the figure 1 circuit will provide an adequate starting point for most applications. the values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capaci- tors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability. the gain of the loop will be increased by increasing r c , and the bandwidth of the loop will be increased by decreasing c c . the output voltage settling behavior is related to the stability of the closed- loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. opti-loop is a registered trademark of linear technology corporation.
20 LTC3737 3737fa a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(c load ). thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in will be operating from a maximum of 4.2v down to a minimum of 2.7v (powered by a single lithium-ion battery). load current requirement is a maximum of 2.5a, but most of the time it will be in a standby mode requiring only 2ma. efficiency at both low and high load currents is important. burst mode operation at light loads is desired. output voltage is 2.5v. the iprg pin will be tied to v in , so the maximum current sense threshold ? v sense(max) is approximately 204mv. maximum duty cycle = v out + + = v vv d in min d () % 93 from figure 2, sf = 57%. rsf v i ds on max sense max out max t ()( ) () () ?.? ? ? . = ? = ? 5 6 09 0 027 a 0.025 ? si3473dv p-channel mosfet is close to this value. the plllpf pin will be left floating, so the LTC3737 will operate at its default frequency of 550khz. for continuous burst mode operation, the required minimum inductor value is: l vv khz v vv vv h min = ? ? ? ? ? ? ? + + ? ? ? ? ? ? = 42 25 550 0 051 0 025 25 03 42 03 140 .C. . . .. .. . applicatio s i for atio wu uu pc board layout checklist when laying out the printed circuit board, use the follow- ing checklist to ensure proper operation of the LTC3737. ? the power loop (input capacitor, mosfet, inductor, output diode, output capacitor) of each channel should be as small as possible and isolated as much as possible from the other channels power loop. it is better to have two separate, smaller valued input capacitors (e.g., two 10 fone for each channel) than it is to have a single larger valued capacitor (e.g., one 22 f) that the channels share with a common connection. ? the signal and power grounds should be kept separate. the signal ground consists of the feedback resistor dividers, i th compensation networks and the sgnd pin. the power grounds consist of the (C) terminal of the input and output capacitors, the anode of the schottky diodes and the pgnd pins. each channel should have its own power ground for its power loop as described above. the power grounds for the two channels should connect together at a common point. it is most impor- tant to keep the ground paths with high switching currents away from each other. ? put the feedback resistors close to the v fb pins. the i th compensation components should also be very close to the LTC3737. ? the current sense traces (sense + and sense C /sw) should be kelvin connections right at the p-channel mosfet source and drain. ? keep the switch nodes (sw1, sw2) and the gate driver nodes (pgate1, pgate2) away from the small-signal components, especially the opposite channels feed- back resistors, i th compensation components and the current sense pins (sense + and sense C /sw).
21 LTC3737 3737fa v fb2 7 24 220pf 100pf 15k 220pf 100pf 15k 1 187k 59k 1 f 118k 59k 59k 118k 22 21 20 19 m1 d1 c1 47 f c3 10 f 2 v in 5v v out1 2.5v 3a c2 47 f m2 l2 2.2 h l1 2.2 h 8 6 10 11 12 pv in2 i th2 track sw2 sense2 + v fb1 iprg1 iprg2 plllpf sgnd v in pgood 18 17 16 15 14 13 23 2 3 4 5 9 sync/mode pgate1 pgnd pgate2 run/ss nc nc i th1 sw1 sense1 + LTC3737euf pv in1 d2 + + v out2 1.8v 3a 3737 ta01 c1, c2: sanyo 6tpa47m c3: taiyo yuden lmk325bj106k-t d1, d2: ir 10bq015 l1, l2: coilcraft d03316p-22 m1, m2: si9803dy 1m 10 ? 2-phase, 750khz, burst mode dual output step-down dc/dc converter typical applicatio s u v fb2 7 24 220pf 100pf 15k 220pf 100pf 15k 1 187k 59k 1 f 118k 59k 59k 118k 22 21 20 19 m1 d1 c1 150 f c3 22 f 2 v in 5v v out1 2.5v 5a c2 150 f m2 l2 1.5 h l1 1.5 h 8 6 10 11 12 c ss 10nf pv in2 i th2 track sw2 sense2 + v fb1 iprg1 iprg2 plllpf sgnd v in pgood 18 17 16 15 14 13 23 2 3 4 5 9 sync/mode pgate1 pgnd pgate2 run/ss nc nc i th1 sw1 sense1 + LTC3737euf pv in1 d2 + + v out2 1.8v 5a 3737 f13 c1, c2: sanyo 4tpb150mc c3: taiyo yuden lmk325bj106k-t d1, d2: sbm540 l1, l2: vishay ihlp-2525cz-01-1.5 m1, m2: fdc602p 10 ? 1m applicatio s i for atio wu uu figure 13. 2-phase, 550khz, dual output step-down dc/dc converter
22 LTC3737 3737fa typical applicatio s u v fb2 7 24 220pf 100pf 10nf 1 f 15k 10k 1m 10 ? 220pf 100pf 15k 1 187k 59k 118k 59k 59k 118k 22 21 20 19 m1 d1 c1 47 f v in 3.3v v out1 2.5v 2 a c2 47 f m2 l2 2.2 h l1 2.2 h 8 6 10 11 12 pv in2 i th2 track sw2 sense2 + v fb1 iprg1 iprg2 plllpf sgnd v in pgood 18 17 16 15 14 13 23 2 3 4 5 9 sync/mode pgate1 pgnd pgate2 run/ss nc nc i th1 sw1 sense1 + LTC3737euf pv in1 d2 + + v out2 1.8v 2a 3737 ta02 c1, c2: sanyo 6tpa47m c3: taiyo yuden lmk325bj106k-t d1, d2: central cmsh1-20ml l1, l2: coilcraft d03316p-22 m1, m2: si9803dy c3 10 f 2 2-phase, synchronizable dual output step-down dc/dc converter v fb2 7 24 220pf 15k 220pf 1 59k 118k 22 21 20 19 m1 d1 c1 150 f c3 10 f 2 v in 3.3v v out 1.8v 8a c2 150 f m2 l2 1.5 h l1 1.5 h 8 6 10 11 12 1 f pv in2 i th2 track sw2 sense2 + v fb1 iprg1 iprg2 plllpf sgnd v in pgood 18 17 16 15 14 13 23 2 3 4 5 9 sync/mode pgate1 pgnd pgate2 run/ss nc nc i th1 sw1 sense1 + LTC3737euf pv in1 d2 + + 3737 ta04 c1, c2: sanyo 4tpr150mc c3: taiyo yuden lmk325bj106k-t d1, d2: sbm540 l1, l2: vishay ihlp-2525cz-01-1.5 m1, m2: fdc602p 1m 59k 118k 10 ? 2-phase, 550khz, single output step-down dc/dc converter (3.3v in to 1.8v out at 8a)
23 LTC3737 3737fa 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)to be approved 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (note 6) 0.38 0.10 24 0.23 typ (4 sides) 23 1 2 bottom viewexposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf24) qfn 1103 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package .337 C .344* (8.560 C 8.738) gn24 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 17 18 19 20 21 22 23 24 15 14 13 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .0075 C .0098 (0.19 C 0.25) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale u package descriptio uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 LTC3737 3737fa lt/tp 0205 1k rev a ? printed in usa ? linear technology corporation 2004 related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com typical applicatio u part number description comments ltc1628/ltc3728 dual high efficiency, 2-phase synchronous constant frequency, standby, 5v and 3.3v ldos, v in to 36v, step down controllers 28-lead ssop ltc1629/ltc3729 20a to 200a polyphase tm high efficiency controllers expandable up to 12 phases, no heat sinks, v in to 36v, 28-lead ssop ltc1702a no r sense tm 2-phase dual synchronous controller 550khz, no sense resistor, gn24, v in to 7v ltc1735 high efficiency synchronous step-down controller burst mode operation, 16-pin narrow ssop, fault protection, 3.5v v in 36v ltc1772 current mode step-down dc/dc controller 2.5v v in 9.8v, i out up to 4a, sot-23 package, 550khz ltc1773 synchronous step-down controller 2.65v v in 8.5v, i out up to 4a, 10-lead msop ltc1778 no r sense synchronous step-down controller current mode operation without sense resistor, fast transient response, 4v v in 36v ltc1872 constant frequency current mode step-up controller 2.5v v in 9.8v, sot-23 package, 550khz ltc1929 constant frequency current mode 2-phase up to 42a, no heat sink, 3.5v v in 36v synchronous controller ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60 a, i sd = <1 a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60 a, i sd = <1 a, tssop-16e package ltc3700 constant frequency step-down controller with ldo regulator 2.65 v in 9.8v, 550khz, 10-lead ssop ltc3701 2-phase, low input voltage dual step-down dc/dc controller 2.5v v in 9.8v, 550khz, pgood, pll, 16-lead ssop ltc3708 2-phase, dual synchronous controller with output tracking constant on-time dual controller, v in up to 36v, very low duty cycle operation, 5mm 5mm qfn package ltc3736 2-phase, dual synchronous controller with output tracking 2.75v v in 9.8v, 0.6v v out v in , 4mm 4mm qfn ltc3736-1 low emi, 2-phase, dual synchronous controller spread spectrum frequency modulation for low noise and emi polyphase and no r sense are trademarks of linear technology corporation. 2-phase, 300khz, resistor sensing, dual output step-down dc/dc converter v fb2 7 24 220pf 100pf 15k r1 0.03 ? 1m 10 ? 1 f 220pf 100pf 15k 1 187k 59k 59k 118k 22 21 20 19 m1 d1 c1 47 f c3 10 f 2 v in 2.75v to 9.8v v out1 2.5v 2a c2 47 f m2 l2 2.2 h l1 2.2 h 8 6 10 11 12 pv in2 i th2 track sw2 sense2 + v fb1 iprg1 iprg2 plllpf sgnd v in pgood 18 17 16 15 14 13 23 2 3 4 5 9 sync/mode pgate1 pgnd pgate2 run/ss nc nc i th1 sw1 sense1 + LTC3737euf pv in1 d2 + + v out2 1.8v 2a 3737 ta03 c1, c2: sanyo 6tpa47m c3: taiyo yuden lmk325bj106k-t d1, d2: central cmsh1-20ml l1, l2: coilcraft d03316p-22 m1, m2: si3867dv r2 0.03 ?

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